About

Biography

My name is Dingbang Liu (刘定邦), a second year graduate student at the School of Computer Science and Technology of Harbin Institute of Technology (Shenzhen), supervised by Prof. Wen Xia. Currently I am doing research on deduplication-based systems. I am interested in computer systems, those built with emerging devices like non-volatile memory and high-speed network in particular.

Education

Master’s Student at Harbin Institute of Technology (Shenzhen)

• September 2022 – now; expected to graduate in March 2025
• Supervised by Prof. Wen Xia

B.Eng. in Computer Science of Technology, Harbin Institute of Technology (Shenzhen)

• September 2018 – June 2022

Research

Alleviating Data Fragmentation in Deduplication Systems

• July 2023 – now
• One version of paper submitted to USENIX ATC 2024 in January
• We propose a restore acceleration approach for deduplication-based storage systems under general scenarios with few additional I/O overhead.
• We study how unique chunks are shared by deduplicated files (i.e., the attributions of chunks) and group chunks with similar attributions. Specifically, we discover and exploit the generational and genetic features in attributions to bound the number of categories while preserving the benefits of classification.
• We piggyback the migration process of garbage collection to migrate chunks based on the categories indicated by the attribution-based classification, hiding the costs of reorganization of chunks in garbage collection.
• Evaluation results suggest that our approach outperforms Capping, a rewriting-based approach, in terms of restore speed, while avoiding decline of deduplication ratio. Our approach can also cooperate with Capping to achieve further restore speedup.

Projects

4th “Loongson Cup” National Student Computer System Capability Challenge (NSCSCC 2020)

• March 2020 – August 2020
• Group project by 4 participants. I am mainly in charge of pipeline implementation.
• Designed and implemented a dual-issue 6-stage pipelined MIPS processor. We did timing analysis for critical paths and optimized for low latency accordingly.
• Multiplication is conducted by a Wallace tree multiplier, divided into two stages and optimized for low latency with CSAs (carry-save adders).
• The final processor is clocked at 88 MHz and the instructions per cycle is 34.4 times that of gs132 (the baseline processor) and awarded the first prize.
• Implemented a controller for VGA and can cooperate with other peripherals by software code.
• Can run pmon (a bootloader provided by the committee) and run software code from pmon.
• Our code is hosted on GitHub. Follow this link for more details.

Honors

Underway

Skills & Interests

• Programming languages: C/C++, Python, Perl, Haskell
• Linux distributions: Arch Linux, Debian
• Languages: Chinese, English, (a rather tiny bit of) French, (also a very tiny bit of) German